Pipeline run

259e9ea2-8fc4-45ba-a29a-71b8ca2b1869

Pipeline LLM cost (USD)

API 1: $0.0081 API 2: $0.0001 API 3: $0.0000 Total: $0.0082

Client output enrichment

v2 Skill cluster · Nature of work · AI index · Tech stack maturity · Evidence · KRA description

SPARSE JD sources · ai_index: jd · nature_of_work: jd · tech_stack_maturity: jd

Nature of work · IO Design

Own IO IP block development end to end: define specs/topologies, build and verify testbenches, run DC/AC/transient/STB/EMIR sims, guide layout and silicon debug, and support post-silicon/customer issues while mentoring junior engineers.

""Take full ownership of End-to-End IP development and support for IO IPs""

Tech stack maturity

Mainstream Modern

AI index (0 = no AI use, 5 = totally AI-dependent · v2.1)

0.00 / 5

· Title match

· Has AI skill

· AI skill (primary)

· AI skill (secondary)

· On AI team

· Builds AI products

vocab breakdown (legacy)

Assistants (×1): —

Frameworks (×2): —

Models / concepts (×3): —

Evidence — skills matched in JD (1)

Apex

Skill cluster (1 dimension groups, role-scoped)

Cross-cutting / unaligned

Apex

Show KRA description ↓

• Take full ownership of End-to-End IP development and support for IO IPs – Define specifications, define topologies, design/verify, guide layout team, post silicon validation, customer support on IP bugs • Mentor junior engineers in block level designs • Create required testbenches and perform DC, AC, Transient, STB, EMIR simulations • Create design documents and drive Design reviews • Be a creative problem solver, and look for innovation in design • Work with cross-geo, cross-vertical teams to understand requirements and communicate resolution • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs • BS + 10 years/ MS + 8 years/ PhD + 6 or more years of experience working on IO Design - GPIO, LVDS, SSTL, HSTL, MIPI • Deep understanding of Standard CMOS, FinFet and SOI technologies • Multiple successful tapeouts in IO IPs • Experience with silicon debug is a big plus • Expert knowledge of Cadence tools – Virtuoso schematic editor, ADE-XL, Spectre • Supervise layout engineers in delivering high quality layouts • Must have good technical verbal and written communication skills and ability to work with cross functional teams is necessary • Be able to collaborate with program and technical design leads on multiple concurrent projects. • Should have excellent problem-solving skills, written & oral communication, teaming & interpersonal skills • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs • Language Fluency – Fluent in English Language – written & verbal • Knowledge of scripting languages like Python/Perl • Familiarity with standard engineering practices like Version Control systems, Configuration Management and Regression process

Signals

Skill —

—

Alias —

—

KRA flutter-developer

0.58

Post-classification

Centroidupdated · n=6

Alias collision log—

New-role queue—

New skills captured1

New KRA capturedyes

Captured for admin review

Apex ↔ FPGA / ASIC Engineer pending

R&R fragment (sim 0.00) ↔ FPGA / ASIC Engineer pending

Status: completed Created: 2026-05-27T17:37:01.218803Z Updated: 2026-05-27T17:37:35.340382Z API 3 duration: 1655 ms

Flow Current 3-step pipeline

1 POST /skills/extract-from-jd

2 POST /skills/extract-details

3 POST /skills/final-role-output

Role Chosen role & resolution

FPGA / ASIC Engineer

domain · Hardware Engineering CASE DOMAIN

slug: fpga-asic-engineer · id: 216 · source: db

Domain=Hardware Engineering; The JD is centered on IO IP development, design/verification, layout support, silicon validation, and Cadence-based IC design work, which aligns strongly with ASIC/analog mixed-signal engineering.

Matched skills

IO IPsGPIOLVDSSSTLHSTLMIPIStandard CMOSFinFetSOICadence toolsVirtuosoADE-XLSpectrePythonPerl

Matched dimensions

IO IP Design and DevelopmentAnalog/Mixed-Signal VerificationLayout Leadership and ReviewPost-Silicon Validation and DebugCross-functional Technical CollaborationDesign Documentation and ReviewsEngineering Mentorship

Matched KRAs

Take full ownership of End-to-End IP developmentDefine specifications, define topologiesdesign/verify, guide layout teampost silicon validation, customer support on IP bugsCreate required testbenchesperform DC, AC, Transient, STB, EMIR simulationsCreate design documents and drive Design reviewsSupervise layout engineers in delivering high quality layoutsCollaborate with program and technical design leadsMentor junior engineers in block level designs

Resolution: in_db — role exists in library; skill↔dim and role↔dim links saved when applicable.

New skills

Skill↔dim saved

Role↔dim saved

Skipped

Job description

Title: Principal Engineer - IO Layout Design

About GlobalFoundries

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Introduction: This position is for IO Layout Engineer who will work on multiple IO IPs. The successful candidate needs to have a solid background in CMOS design, End-to-end Analog/IO IP development experience, and needs to be a team player with a solution-oriented approach.

Your Job

• Take full ownership of End-to-End IP development and support for IO IPs – Define specifications, define topologies, design/verify, guide layout team, post silicon validation, customer support on IP bugs
• Mentor junior engineers in block level designs
• Create required testbenches and perform DC, AC, Transient, STB, EMIR simulations
• Create design documents and drive Design reviews
• Be a creative problem solver, and look for innovation in design
• Work with cross-geo, cross-vertical teams to understand requirements and communicate resolution


Other Responsibilities

• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs


Required Qualifications

• BS + 10 years/ MS + 8 years/ PhD + 6 or more years of experience working on IO Design - GPIO, LVDS, SSTL, HSTL, MIPI
• Deep understanding of Standard CMOS, FinFet and SOI technologies
• Multiple successful tapeouts in IO IPs
• Experience with silicon debug is a big plus
• Expert knowledge of Cadence tools – Virtuoso schematic editor, ADE-XL, Spectre
• Supervise layout engineers in delivering high quality layouts
• Must have good technical verbal and written communication skills and ability to work with cross functional teams is necessary
• Be able to collaborate with program and technical design leads on multiple concurrent projects. 
• Should have excellent problem-solving skills, written & oral communication, teaming & interpersonal skills
• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs
• Language Fluency – Fluent in English Language – written & verbal


Preferred Qualifications

• Knowledge of scripting languages like Python/Perl
• Familiarity with standard engineering practices like Version Control systems, Configuration Management and Regression process


GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard.

As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.

All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia

Skills from this JD

Each row merges API 1 extraction, API 2 library match / v3 orchestration (dimensions + locked dims), and API 3 persistence tags.

Apex Secondary New / orchestrated API 3: new canonical path (new) New / unmatched skill (orchestrated in API 2)

Skill enrichment (orchestrator / LLM)

No Stage 7 enrichment blob on this skill (orchestrator skipped enrichment).

Derived legacy fields

Category: Programming Languages
Sub-category: general
Skill nature: LANGUAGE
Volatility: MEDIUM
Typical lifespan: MULTI_YEAR
Version strategy: UNVERSIONED

Library artifacts (this run)

Kind	Detail	DB id
canonical_skill_proposed	Apex \| type=Programming Languages subtype=general nature=LANGUAGE lifespan=MULTI_YEAR

nano JD Parser — gpt-4.1-nano click to toggle

RolePrincipal Engineer - IO Layout Design

CompanyGlobalFoundries

ExperienceBS + 10 years/ MS + 8 years/ PhD + 6 or more years of experience

DomainSemiconductors

JD type pass

Show raw JSON

{
  "JD_type": "pass",
  "about_company": {
    "source_marker": {
      "first_5_words": "GlobalFoundries is a leading",
      "last_5_words": "shape their markets."
    },
    "text": "GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world\u2019s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets.",
    "word_count": 52
  },
  "certifications": [],
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  "ctc": null,
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  "experience": {
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    "min": 6,
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  },
  "job_locations": [],
  "role": "Principal Engineer - IO Layout Design",
  "role_aliases": [
    "IO Layout Engineer",
    "Layout Design Engineer",
    "Principal Engineer"
  ],
  "role_archetype": "Engineering",
  "roles_and_responsibilities": [
    {
      "bullet_count": 6,
      "heading": "Your Job",
      "heading_was_present": true,
      "source_marker": {
        "first_5_words": "\u2022 Take full ownership of",
        "last_5_words": "and communicate resolution"
      },
      "text": "\u2022 Take full ownership of End-to-End IP development and support for IO IPs \u2013 Define specifications, define topologies, design/verify, guide layout team, post silicon validation, customer support on IP bugs\n\u2022 Mentor junior engineers in block level designs\n\u2022 Create required testbenches and perform DC, AC, Transient, STB, EMIR simulations\n\u2022 Create design documents and drive Design reviews\n\u2022 Be a creative problem solver, and look for innovation in design\n\u2022 Work with cross-geo, cross-vertical teams to understand requirements and communicate resolution",
      "word_count": 83
    },
    {
      "bullet_count": 1,
      "heading": "Other Responsibilities",
      "heading_was_present": true,
      "source_marker": {
        "first_5_words": "\u2022 Perform all activities in",
        "last_5_words": "Health, Safety \u0026 Security requirements"
      },
      "text": "\u2022 Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety \u0026 Security requirements and programs",
      "word_count": 22
    },
    {
      "bullet_count": 11,
      "heading": "Required Qualifications",
      "heading_was_present": true,
      "source_marker": {
        "first_5_words": "\u2022 BS + 10 years/ MS +",
        "last_5_words": "and verbal"
      },
      "text": "\u2022 BS + 10 years/ MS + 8 years/ PhD + 6 or more years of experience working on IO Design - GPIO, LVDS, SSTL, HSTL, MIPI\n\u2022 Deep understanding of Standard CMOS, FinFet and SOI technologies\n\u2022 Multiple successful tapeouts in IO IPs\n\u2022 Experience with silicon debug is a big plus\n\u2022 Expert knowledge of Cadence tools \u2013 Virtuoso schematic editor, ADE-XL, Spectre\n\u2022 Supervise layout engineers in delivering high quality layouts\n\u2022 Must have good technical verbal and written communication skills and ability to work with cross functional teams is necessary\n\u2022 Be able to collaborate with program and technical design leads on multiple concurrent projects.\n\u2022 Should have excellent problem-solving skills, written \u0026 oral communication, teaming \u0026 interpersonal skills\n\u2022 Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety \u0026 Security requirements and programs\n\u2022 Language Fluency \u2013 Fluent in English Language \u2013 written \u0026 verbal",
      "word_count": 157
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    {
      "bullet_count": 2,
      "heading": "Preferred Qualifications",
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      "source_marker": {
        "first_5_words": "\u2022 Knowledge of scripting languages",
        "last_5_words": "Management and Regression process"
      },
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      "word_count": 24
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  ],
  "urls": [
    {
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      "url": "https://gf.com/about-us/careers/opportunities-asia"
    }
  ]
}

API 1 — extract-from-jd click to toggle

{
  "final_skills": [
    {
      "is_primary": false,
      "skill_name": "Apex"
    }
  ],
  "jd_role": {
    "display_name": "Principal Engineer - IO Layout Design",
    "rationale": null,
    "role_aliases": [
      "IO Layout Engineer",
      "Layout Design Engineer",
      "Principal Engineer"
    ],
    "role_archetype": "Engineering",
    "slug": ""
  },
  "nano_parsed": {
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    "about_company": {
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        "first_5_words": "GlobalFoundries is a leading",
        "last_5_words": "shape their markets."
      },
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      "word_count": 52
    },
    "certifications": [],
    "company_name": "GlobalFoundries",
    "ctc": null,
    "domain": {
      "primary": {
        "aliases": [
          "Chip Manufacturing",
          "Microelectronics"
        ],
        "domain": "Semiconductors"
      },
      "secondary": null
    },
    "education": [],
    "experience": {
      "max": 10,
      "min": 6,
      "raw": "BS + 10 years/ MS + 8 years/ PhD + 6 or more years of experience"
    },
    "job_locations": [],
    "role": "Principal Engineer - IO Layout Design",
    "role_aliases": [
      "IO Layout Engineer",
      "Layout Design Engineer",
      "Principal Engineer"
    ],
    "role_archetype": "Engineering",
    "roles_and_responsibilities": [
      {
        "bullet_count": 6,
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        "source_marker": {
          "first_5_words": "\u2022 Take full ownership of",
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        "word_count": 83
      },
      {
        "bullet_count": 1,
        "heading": "Other Responsibilities",
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        "source_marker": {
          "first_5_words": "\u2022 Perform all activities in",
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        "bullet_count": 11,
        "heading": "Required Qualifications",
        "heading_was_present": true,
        "source_marker": {
          "first_5_words": "\u2022 BS + 10 years/ MS +",
          "last_5_words": "and verbal"
        },
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        "word_count": 157
      },
      {
        "bullet_count": 2,
        "heading": "Preferred Qualifications",
        "heading_was_present": true,
        "source_marker": {
          "first_5_words": "\u2022 Knowledge of scripting languages",
          "last_5_words": "Management and Regression process"
        },
        "text": "\u2022 Knowledge of scripting languages like Python/Perl\n\u2022 Familiarity with standard engineering practices like Version Control systems, Configuration Management and Regression process",
        "word_count": 24
      }
    ],
    "urls": [
      {
        "type": "careers",
        "url": "https://gf.com/about-us/careers/opportunities-asia"
      }
    ]
  },
  "rejected": false,
  "rejection_reason": null,
  "run_id": "259e9ea2-8fc4-45ba-a29a-71b8ca2b1869",
  "stage3_signals": {
    "alias_found": false,
    "alias_match_roles": [],
    "kra_match_roles": [
      {
        "display_name": "Flutter Developer",
        "kra_matches": [
          {
            "kra_text": "collaborate with design, product, and backend teams",
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          },
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          },
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        ],
        "matched_count": null,
        "matched_skills": null,
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        "total_count": null
      },
      {
        "display_name": "Cloud Architect",
        "kra_matches": [
          {
            "kra_text": "Conducts architecture reviews, approves technical design documents, and guides engineering teams through cloud migration and modernization projects.",
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            "similarity": 0.6121
          },
          {
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          },
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          }
        ],
        "matched_count": null,
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        "role_id": 9,
        "score": 0.5387,
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      },
      {
        "display_name": "Angular Frontend Developer",
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          },
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          },
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        ],
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        "matched_skills": null,
        "role_id": 90,
        "score": 0.521,
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        "total_count": null
      },
      {
        "display_name": "Fullstack Developer",
        "kra_matches": [
          {
            "kra_text": "Works closely with product managers and UX designers to translate requirements and wireframes into working software features through iterative development.",
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          },
          {
            "kra_text": "Works closely with product managers and UX designers to translate requirements and wireframes into working software features through iterative development.",
            "sentence": "Work with cross-geo, cross-vertical teams to understand requirements and communicate resolution",
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          },
          {
            "kra_text": "Works closely with product managers and UX designers to translate requirements and wireframes into working software features through iterative development.",
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          }
        ],
        "matched_count": null,
        "matched_skills": null,
        "role_id": 15,
        "score": 0.4905,
        "slug": "full-stack-engineer",
        "total_count": null
      },
      {
        "display_name": "React Frontend Developer",
        "kra_matches": [
          {
            "kra_text": "translate product and design requirements",
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          },
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            "sentence": "Work with cross-geo, cross-vertical teams to understand requirements and communicate resolution",
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          }
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        "role_id": 89,
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      }
    ],
    "skill_match_roles": []
  },
  "stage4_decision": {
    "alias_collision_detected": false,
    "case": "DOMAIN",
    "chosen_role": {
      "display_name": "FPGA / ASIC Engineer",
      "kra_matches": null,
      "matched_count": null,
      "matched_skills": null,
      "role_id": 216,
      "score": 0.98,
      "slug": "fpga-asic-engineer",
      "total_count": null
    },
    "confidence": 0.98,
    "is_new_role": false,
    "llm2_fired": false,
    "llm2_reasoning": null,
    "matched_dimensions": [
      "IO IP Design and Development",
      "Analog/Mixed-Signal Verification",
      "Layout Leadership and Review",
      "Post-Silicon Validation and Debug",
      "Cross-functional Technical Collaboration",
      "Design Documentation and Reviews",
      "Engineering Mentorship"
    ],
    "matched_kras": [
      "Take full ownership of End-to-End IP development",
      "Define specifications, define topologies",
      "design/verify, guide layout team",
      "post silicon validation, customer support on IP bugs",
      "Create required testbenches",
      "perform DC, AC, Transient, STB, EMIR simulations",
      "Create design documents and drive Design reviews",
      "Supervise layout engineers in delivering high quality layouts",
      "Collaborate with program and technical design leads",
      "Mentor junior engineers in block level designs"
    ],
    "matched_skills": [
      "IO IPs",
      "GPIO",
      "LVDS",
      "SSTL",
      "HSTL",
      "MIPI",
      "Standard CMOS",
      "FinFet",
      "SOI",
      "Cadence tools",
      "Virtuoso",
      "ADE-XL",
      "Spectre",
      "Python",
      "Perl"
    ],
    "new_role_display_name": null,
    "new_role_slug": null,
    "queued": false,
    "reasoning": "Domain=Hardware Engineering; The JD is centered on IO IP development, design/verification, layout support, silicon validation, and Cadence-based IC design work, which aligns strongly with ASIC/analog mixed-signal engineering.",
    "sub_role": null
  },
  "stage5_updates": {
    "centroid_n_after": 6,
    "centroid_updated": true,
    "collision_log_id": null,
    "new_kra_attached": {
      "best_kra_similarity": 0.0,
      "queue_id": 1876,
      "r_and_r_preview": "\u2022 Take full ownership of End-to-End IP development and support for IO IPs \u2013 Define specifications, define topologies, design/verify, guide layout team, post silicon validation, customer support on IP ",
      "role_display_name": "FPGA / ASIC Engineer",
      "role_slug": "fpga-asic-engineer",
      "status": "pending"
    },
    "new_skills_attached": [
      {
        "is_primary": false,
        "queue_id": 24449,
        "role_display_name": "FPGA / ASIC Engineer",
        "role_slug": "fpga-asic-engineer",
        "skill_name": "Apex",
        "status": "pending"
      }
    ],
    "queue_entry_id": null,
    "v3_pipeline_triggered": false,
    "v3_role_slug": null,
    "v3_run_id": null
  }
}

API 2 — extract-details

{
  "alias_matches": [],
  "candidate_roles": [],
  "chosen_role": {
    "display_name": "FPGA / ASIC Engineer",
    "id": 216,
    "rationale": "Domain=Hardware Engineering; The JD is centered on IO IP development, design/verification, layout support, silicon validation, and Cadence-based IC design work, which aligns strongly with ASIC/analog mixed-signal engineering.",
    "role_archetype": null,
    "slug": "fpga-asic-engineer",
    "source": "db"
  },
  "dimensions": [],
  "input_final_skills": [
    "Apex"
  ],
  "input_llm_skills": [
    "Apex"
  ],
  "new_aliases_persisted": 0,
  "run_id": "259e9ea2-8fc4-45ba-a29a-71b8ca2b1869",
  "skills_detail": [
    {
      "aliases_in_db": [],
      "canonical": null,
      "dimensions": [],
      "input_skill": "Apex",
      "matched_via": null,
      "new_alias_persisted": false,
      "new_alias_text": null,
      "new_skill_meta": {
        "derived": {
          "category": "Programming Languages",
          "skill_nature": "LANGUAGE",
          "sub_category": "general",
          "typical_lifespan": "MULTI_YEAR",
          "version_strategy": "UNVERSIONED",
          "volatility": "MEDIUM"
        },
        "enrichment": null,
        "keep_log": [],
        "locked_dimensions": [],
        "merge_log": [],
        "placed": null,
        "relationships": null,
        "skill_id": "apex",
        "split_log": [],
        "typed": null,
        "warnings": []
      },
      "source_tag": "llm",
      "was_in_llm_skills": true
    }
  ],
  "unmatched_skills": [
    "Apex"
  ]
}

API 3 — final-role-output

{
  "chosen_role": {
    "display_name": "FPGA / ASIC Engineer",
    "id": 216,
    "rationale": "Domain=Hardware Engineering; The JD is centered on IO IP development, design/verification, layout support, silicon validation, and Cadence-based IC design work, which aligns strongly with ASIC/analog mixed-signal engineering.",
    "role_archetype": null,
    "slug": "fpga-asic-engineer",
    "source": "db"
  },
  "chosen_role_resolution": "in_db",
  "final_input_skills": [
    {
      "skill": "Apex",
      "tag": "new"
    }
  ],
  "llm_cost_api1_usd": null,
  "llm_cost_api2_usd": null,
  "llm_cost_api3_usd": null,
  "llm_cost_total_usd": null,
  "persistence": {
    "items": [],
    "new_skills_created": 0,
    "role_dimension_saved": 0,
    "skill_dimension_saved": 0,
    "skipped": 0
  },
  "planner_output": null,
  "run_id": "259e9ea2-8fc4-45ba-a29a-71b8ca2b1869"
}