Pipeline run

279ceb3e-5f4d-4a4d-b994-28dc4a9fdb81

Pipeline LLM cost (USD)

API 1: $0.0070 API 2: $0.0003 API 3: $0.0000 Total: $0.0073

Client output enrichment

v2 Skill cluster · Nature of work · AI index · Tech stack maturity · Evidence · KRA description

Nature of work · STA / Timing Closure

Own chip-level STA and timing closure: build/extend constraints, close coverage gaps, analyze sign-off timing margins and signal integrity, and review STA reports before tapeout while coordinating fixes with PD and RTL teams.

"Final reviewer for STA reports before submission to manufacturing"

Tech stack maturity

Mainstream Modern

AI index (0 = no AI use, 5 = totally AI-dependent · v2.1)

0.00 / 5

· Title match

· Has AI skill

· AI skill (primary)

· AI skill (secondary)

· On AI team

· Builds AI products

vocab breakdown (legacy)

Assistants (×1): —

Frameworks (×2): —

Models / concepts (×3): —

Evidence — skills matched in JD (7)

STA Timing Closure Signal Integrity Physical Design RTL ECO PPAS

Skill cluster (1 dimension groups, role-scoped)

Cross-cutting / unaligned

STA Timing Closure Signal Integrity Physical Design RTL ECO PPAS

Show KRA description ↓

Develop functional, test constraints from scratch Identify constraints required beyond traditional/available, provide them as needed Close constraint coverage loss/issues Improve PPAS by but not limited to improvements in Methodology, Analysis and ECO Understand chip level clock, reset architecture and drive easy timing closure Derive and is accountable for sign-off timing margins Final reviewer for STA reports before submission to manufacturing Signal integrity analysis & fix Do bottleneck analysis, Report abstract data, prioritize fixation methods and identify methods for margin improvement Coordinate with Full chip Physical design team Coordinate with RTL design/architecture team An individual contributor, knows requirements to execute his/her responsibilities and seamlessly drives needed coordination among technical team members to constantly achieve better PPAS

Signals

Skill —

—

Alias —

—

KRA flutter-developer

0.49

Post-classification

Centroidupdated · n=4

Alias collision log—

New-role queue—

New skills captured7

New KRA capturedyes

Captured for admin review

STA primary ↔ FPGA / ASIC Engineer pending

Timing Closure primary ↔ FPGA / ASIC Engineer pending

Signal Integrity primary ↔ FPGA / ASIC Engineer pending

Physical Design primary ↔ FPGA / ASIC Engineer pending

RTL primary ↔ FPGA / ASIC Engineer pending

ECO primary ↔ FPGA / ASIC Engineer pending

PPAS primary ↔ FPGA / ASIC Engineer pending

R&R fragment (sim 0.00) ↔ FPGA / ASIC Engineer pending

Status: completed Created: 2026-05-27T17:34:45.304140Z Updated: 2026-05-27T17:36:02.607574Z API 3 duration: 1811 ms

Flow Current 3-step pipeline

1 POST /skills/extract-from-jd

2 POST /skills/extract-details

3 POST /skills/final-role-output

Role Chosen role & resolution

FPGA / ASIC Engineer

domain · Hardware Engineering CASE DOMAIN

slug: fpga-asic-engineer · id: 216 · source: db

Domain=Hardware Engineering; The JD is centered on chip-level static timing analysis, constraints, sign-off timing margins, ECOs, and coordination with physical design and RTL teams, which best matches an FPGA/ASIC engineering role.

Matched skills

STAPPASECOchip level clockreset architecturesign-off timing marginsSTA reportsSignal integrity analysis

Matched dimensions

Static Timing AnalysisTiming ClosureConstraint DevelopmentChip-Level SignoffSignal IntegrityCross-Functional Coordination

Matched KRAs

Develop functional, test constraints from scratchClose constraint coverage loss/issuesImprove PPAS through methodology, analysis and ECODrive easy timing closureDerive and be accountable for sign-off timing marginsFinal reviewer for STA reports before submission to manufacturingSignal integrity analysis & fixCoordinate with Full chip Physical design teamCoordinate with RTL design/architecture team

Resolution: in_db — role exists in library; skill↔dim and role↔dim links saved when applicable.

New skills

Skill↔dim saved

Role↔dim saved

Skipped

Job description

Req. ID: 239781 Micron Technology’s vision is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community.   Role   In this role as a Principal STA Engineer in Micron’s Non-Volatile Engineering Group, you will be responsible for crafting next generation ASIC products for Micron on most recent technology nodes. Responsibilities  Develop functional, test constraints from scratch   Identify constraints required beyond traditional/available, provide them as needed   Close constraint coverage loss/issues   Improve PPAS by but not limited to improvements in Methodology, Analysis and ECO   Understand chip level clock, reset architecture and drive easy timing closure   Derive and is accountable for sign-off timing margins   Final reviewer for STA reports before submission to manufacturing   Signal integrity analysis & fix   Do bottleneck analysis, Report abstract data, prioritize fixation methods and identify methods for margin improvement   Coordinate with Full chip Physical design team   Coordinate with RTL design/architecture team   An individual contributor, knows requirements to execute his/her responsibilities and seamlessly drives needed coordination among technical team members to constantly achieve better PPAS    Requirements    A minimum of 13-19 years of Static timing analysis/RTL development/RTL Synthesis experience   Very strong STA fundamentals, Signal integrity fundamentals   The specialist in Synopsys Design Constraints (SDC) constructs, issues, customized constraint delivery specialist   Lower power timing closure methodology experience   Fully aware of different DFT modes, has developed/modified/merged constraints for DFT modes   Specialist in at least one EDA tool, but is tool/methodology/flow agnostic with great functional proven experience   Very good proficiency in at least one programming language like TCL/PERL/Python   Has done at least one multi-partition/multi-million gate System on Chip / Test chip as top level hands-on STA lead.   Leads by example, works on ambitious, results-oriented schedule & does data driven, flawless aligned decision making   Well aware of Silicon development and Post-silicon work flows   Knowledge of abstract timing models, creation of/issue/limitations of.   Excellent debug , analytical skills   Specialist in collaborating in a team of multi-functional, geographically distributed members with highly diverse skill levels.   Bachelors of Engineering/Master of Technology in E&C/Electrical/Computer Science.    Preferred Skills:    Strong verbal, interpersonal skills   Spice simulation experience   Strong electronic circuit fundamentals, Circuit level timing fixes   Post-Silicon timing debug experience   RTL coding/verification experience   P&R implementation exposure    About Us   As the leader in innovative memory solutions, Micron is helping the world make sense of data by delivering technology that is transforming how the world uses information. Through our global brands — Micron, Crucial and Ballistix — we offer the industry’s broadest portfolio. We are the only company manufacturing today’s major memory and storage technologies: DRAM, NAND, NOR and 3D XPoint™ memory. Our solutions are purpose built to leverage the value of data to unlock financial insights, accelerate scientific breakthroughs and enhance communication around the world.   Micron Benefits   Employee Rewards Program, Healthcare, Paid time off (Combined Sick and Vacation Time), Retirement savings plans, Paid maternity/paternity leave, Employee Assistance Program, Professional development training, Workplace wellness programs, Micron Health Clinic (Boise only), Fitness Center / Activity rooms (Boise only), Tuition Reimbursement, Micron Corporate Discounts, Casual Dress attire. We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law. This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices. Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters. To request assistance with the application process, please contact Micron’s Human Resources Department at 1-800-336-8918 (or 208-368-4748). We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law. This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices. Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters. To request assistance with the application process, please contact Micron’s Human Resources Department at 1-800-336-8918 (or 208-368-4748). Keywords: Hyderabad || Telangana (IN-TG) || India (IN) || NVE (Non-Volatile Engineering Group) || Experienced || Regular || Engineering || ||

Skills from this JD

Each row merges API 1 extraction, API 2 library match / v3 orchestration (dimensions + locked dims), and API 3 persistence tags.

STA Primary New / orchestrated API 3: new canonical path (new) New / unmatched skill (orchestrated in API 2)

Skill enrichment (orchestrator / LLM)