Pipeline run

{
  "final_skills": [
    {
      "is_primary": true,
      "skill_name": "RTL"
    },
    {
      "is_primary": true,
      "skill_name": "LPDDR5"
    },
    {
      "is_primary": true,
      "skill_name": "DDR5"
    },
    {
      "is_primary": true,
      "skill_name": "GDDR6"
    },
    {
      "is_primary": true,
      "skill_name": "HBM2"
    },
    {
      "is_primary": true,
      "skill_name": "HBM3"
    }
  ],
  "jd_role": {
    "display_name": "RTL Frontend Engineer",
    "rationale": null,
    "role_aliases": [
      "Frontend Engineer",
      "RTL Engineer",
      "Digital Design Engineer"
    ],
    "role_archetype": "Engineering",
    "slug": ""
  },
  "nano_parsed": {
    "JD_type": "pass",
    "about_company": {
      "source_marker": {
        "first_5_words": "At Xilinx, we are leading",
        "last_5_words": "the way we live and work."
      },
      "text": "At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? We develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible. Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the beginning, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world\u0027s first 5G networks, we empower the world\u0027s builders and visionaries whose ideas solve every day problems and improve people\u0027s lives. If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.",
      "word_count": 239
    },
    "certifications": [],
    "company_name": "Xilinx",
    "ctc": null,
    "domain": {
      "primary": {
        "aliases": [
          "SaaS",
          "Product Companies"
        ],
        "domain": "Software \u0026 SaaS Products"
      },
      "secondary": null
    },
    "education": [
      {
        "level": "Master\u0027s",
        "qualification": "MTECH - Equivalent",
        "raw": "MTech or Equivalent",
        "requirement": "required"
      }
    ],
    "experience": {
      "max": 1,
      "min": 0,
      "raw": "0-1yrs"
    },
    "job_locations": [
      {
        "aliases": [
          "Hyderabad, India"
        ],
        "city": "Hyderabad",
        "country": "India",
        "state": null,
        "work_mode": null
      }
    ],
    "role": "RTL Frontend Engineer",
    "role_aliases": [
      "Frontend Engineer",
      "RTL Engineer",
      "Digital Design Engineer"
    ],
    "role_archetype": "Engineering",
    "roles_and_responsibilities": [
      {
        "bullet_count": 0,
        "heading": "Role Overview",
        "heading_was_present": false,
        "source_marker": {
          "first_5_words": "Be part of Xilinx\u0027s analog/mixed",
          "last_5_words": "existing software design models."
        },
        "text": "Be part of Xilinx\u0027s analog/mixed signal IP design team responsible for the design and development of next generation IOs, high speed memory (LPDDR5, DDR5, gDDR6, HBM2/HBM3..) solutions. Candidate will be involved in Creating software models for cutting edge AMS design components. Developing RTL models for AMS design components that align to Xilinx internal and Industry standard work flows. Creating test bench schemes to ensure design integrity across design hierarchies. Interacting and closing discussions with diversified teams including design and verification teams, applications and software teams, IP release team. Working on new modeling schemes that are light on software and yet present full feature set utilization to customer. Debugging and enhancing existing software design models.",
        "word_count": 116
      }
    ],
    "urls": []
  },
  "rejected": false,
  "rejection_reason": null,
  "run_id": "5044a1cf-344b-4676-955a-98d9c1915d09",
  "stage3_signals": {
    "alias_found": true,
    "alias_match_roles": [
      {
        "display_name": "Frontend Developer",
        "kra_matches": null,
        "matched_count": null,
        "matched_skills": null,
        "role_id": 7,
        "score": 1.0,
        "slug": "frontend-engineer",
        "total_count": null
      }
    ],
    "kra_match_roles": [
      {
        "display_name": "Angular Frontend Developer",
        "kra_matches": [
          {
            "kra_text": "collaboration with design and QA",
            "sentence": "Interacting and closing discussions with diversified teams including design and verification teams, applications and software teams, IP release team.",
            "similarity": 0.5111
          },
          {
            "kra_text": "collaboration with design and QA",
            "sentence": "Debugging and enhancing existing software design models.",
            "similarity": 0.4679
          },
          {
            "kra_text": "collaboration with design and QA",
            "sentence": "Creating test bench schemes to ensure design integrity across design hierarchies.",
            "similarity": 0.4425
          }
        ],
        "matched_count": null,
        "matched_skills": null,
        "role_id": 90,
        "score": 0.4739,
        "slug": "angular-frontend-developer",
        "total_count": null
      },
      {
        "display_name": "Fullstack Developer",
        "kra_matches": [
          {
            "kra_text": "Works closely with product managers and UX designers to translate requirements and wireframes into working software features through iterative development.",
            "sentence": "Interacting and closing discussions with diversified teams including design and verification teams, applications and software teams, IP release team.",
            "similarity": 0.4985
          },
          {
            "kra_text": "Works closely with product managers and UX designers to translate requirements and wireframes into working software features through iterative development.",
            "sentence": "Debugging and enhancing existing software design models.",
            "similarity": 0.4677
          },
          {
            "kra_text": "Works closely with product managers and UX designers to translate requirements and wireframes into working software features through iterative development.",
            "sentence": "Working on new modeling schemes that are light on software and yet present full feature set utilization to customer.",
            "similarity": 0.4521
          }
        ],
        "matched_count": null,
        "matched_skills": null,
        "role_id": 15,
        "score": 0.4728,
        "slug": "full-stack-engineer",
        "total_count": null
      },
      {
        "display_name": "Frontend Developer",
        "kra_matches": [
          {
            "kra_text": "Collaborates with UX designers to refine interaction details, animations, responsive breakpoints, and micro-interaction behavior.",
            "sentence": "Interacting and closing discussions with diversified teams including design and verification teams, applications and software teams, IP release team.",
            "similarity": 0.4695
          },
          {
            "kra_text": "Collaborates with UX designers to refine interaction details, animations, responsive breakpoints, and micro-interaction behavior.",
            "sentence": "Debugging and enhancing existing software design models.",
            "similarity": 0.4693
          },
          {
            "kra_text": "Maintains reusable component libraries, design system tokens, and shared UI patterns across the application to ensure visual and behavioral consistency.",
            "sentence": "Creating test bench schemes to ensure design integrity across design hierarchies.",
            "similarity": 0.4355
          }
        ],
        "matched_count": null,
        "matched_skills": null,
        "role_id": 7,
        "score": 0.4581,
        "slug": "frontend-engineer",
        "total_count": null
      },
      {
        "display_name": "Flutter Developer",
        "kra_matches": [
          {
            "kra_text": "collaborate with design, product, and backend teams",
            "sentence": "Interacting and closing discussions with diversified teams including design and verification teams, applications and software teams, IP release team.",
            "similarity": 0.5532
          },
          {
            "kra_text": "collaborate with design, product, and backend teams",
            "sentence": "Debugging and enhancing existing software design models.",
            "similarity": 0.4091
          },
          {
            "kra_text": "translate product and design requirements",
            "sentence": "Developing RTL models for AMS design components that align to Xilinx internal and Industry standard work flows.",
            "similarity": 0.395
          }
        ],
        "matched_count": null,
        "matched_skills": null,
        "role_id": 74,
        "score": 0.4524,
        "slug": "flutter-developer",
        "total_count": null
      },
      {
        "display_name": "Pega Developer",
        "kra_matches": [
          {
            "kra_text": "user interaction design and refinement",
            "sentence": "Debugging and enhancing existing software design models.",
            "similarity": 0.4929
          },
          {
            "kra_text": "user interaction design and refinement",
            "sentence": "Interacting and closing discussions with diversified teams including design and verification teams, applications and software teams, IP release team.",
            "similarity": 0.4478
          },
          {
            "kra_text": "flow, rule, and integration testing",
            "sentence": "Creating test bench schemes to ensure design integrity across design hierarchies.",
            "similarity": 0.4089
          }
        ],
        "matched_count": null,
        "matched_skills": null,
        "role_id": 24,
        "score": 0.4499,
        "slug": "pega-developer",
        "total_count": null
      }
    ],
    "skill_match_roles": []
  },
  "stage4_decision": {
    "alias_collision_detected": false,
    "case": "A",
    "chosen_role": {
      "display_name": "Frontend Developer",
      "kra_matches": null,
      "matched_count": null,
      "matched_skills": null,
      "role_id": 7,
      "score": 1.0,
      "slug": "frontend-engineer",
      "total_count": null
    },
    "confidence": 1.0,
    "is_new_role": false,
    "llm2_fired": false,
    "llm2_reasoning": null,
    "matched_dimensions": [],
    "matched_kras": [],
    "matched_skills": [],
    "new_role_display_name": null,
    "new_role_slug": null,
    "queued": false,
    "reasoning": "Exact alias hit on frontend-engineer (1.0) \u2014 no other alias at this confidence; skill_top absent does not contradict",
    "sub_role": null
  },
  "stage5_updates": {
    "centroid_n_after": 258,
    "centroid_updated": true,
    "collision_log_id": null,
    "new_kra_attached": null,
    "new_skills_attached": [
      {
        "is_primary": true,
        "queue_id": 12653,
        "role_display_name": "Frontend Developer",
        "role_slug": "frontend-engineer",
        "skill_name": "RTL",
        "status": "pending"
      },
      {
        "is_primary": true,
        "queue_id": 12654,
        "role_display_name": "Frontend Developer",
        "role_slug": "frontend-engineer",
        "skill_name": "LPDDR5",
        "status": "pending"
      },
      {
        "is_primary": true,
        "queue_id": 12655,
        "role_display_name": "Frontend Developer",
        "role_slug": "frontend-engineer",
        "skill_name": "DDR5",
        "status": "pending"
      },
      {
        "is_primary": true,
        "queue_id": 12656,
        "role_display_name": "Frontend Developer",
        "role_slug": "frontend-engineer",
        "skill_name": "GDDR6",
        "status": "pending"
      },
      {
        "is_primary": true,
        "queue_id": 12657,
        "role_display_name": "Frontend Developer",
        "role_slug": "frontend-engineer",
        "skill_name": "HBM2",
        "status": "pending"
      },
      {
        "is_primary": true,
        "queue_id": 12658,
        "role_display_name": "Frontend Developer",
        "role_slug": "frontend-engineer",
        "skill_name": "HBM3",
        "status": "pending"
      }
    ],
    "queue_entry_id": null,
    "v3_pipeline_triggered": false,
    "v3_role_slug": null,
    "v3_run_id": null
  }
}

{
  "alias_matches": [],
  "candidate_roles": [],
  "chosen_role": {
    "display_name": "Frontend Developer",
    "id": 7,
    "rationale": "Exact alias hit on frontend-engineer (1.0) \u2014 no other alias at this confidence; skill_top absent does not contradict",
    "role_archetype": null,
    "slug": "frontend-engineer",
    "source": "db"
  },
  "dimensions": [],
  "input_final_skills": [
    "RTL",
    "LPDDR5",
    "DDR5",
    "GDDR6",
    "HBM2",
    "HBM3"
  ],
  "input_llm_skills": [
    "RTL",
    "LPDDR5",
    "DDR5",
    "GDDR6",
    "HBM2",
    "HBM3"
  ],
  "new_aliases_persisted": 0,
  "run_id": "5044a1cf-344b-4676-955a-98d9c1915d09",
  "skills_detail": [
    {
      "aliases_in_db": [],
      "canonical": null,
      "dimensions": [],
      "input_skill": "RTL",
      "matched_via": null,
      "new_alias_persisted": false,
      "new_alias_text": null,
      "new_skill_meta": {
        "derived": {
          "category": "Concepts",
          "skill_nature": "CONCEPT",
          "sub_category": "general",
          "typical_lifespan": "MULTI_YEAR",
          "version_strategy": "UNVERSIONED",
          "volatility": "MEDIUM"
        },
        "enrichment": null,
        "keep_log": [],
        "locked_dimensions": [],
        "merge_log": [],
        "placed": null,
        "relationships": null,
        "skill_id": "rtl",
        "split_log": [],
        "typed": null,
        "warnings": []
      },
      "source_tag": "llm",
      "was_in_llm_skills": true
    },
    {
      "aliases_in_db": [],
      "canonical": null,
      "dimensions": [],
      "input_skill": "LPDDR5",
      "matched_via": null,
      "new_alias_persisted": false,
      "new_alias_text": null,
      "new_skill_meta": {
        "derived": {
          "category": "Memory Technologies",
          "skill_nature": "TOOL",
          "sub_category": "general",
          "typical_lifespan": "SHORT_LIVED",
          "version_strategy": "VERSIONED",
          "volatility": "FAST"
        },
        "enrichment": null,
        "keep_log": [],
        "locked_dimensions": [],
        "merge_log": [],
        "placed": null,
        "relationships": null,
        "skill_id": "lpddr5",
        "split_log": [],
        "typed": null,
        "warnings": []
      },
      "source_tag": "llm",
      "was_in_llm_skills": true
    },
    {
      "aliases_in_db": [],
      "canonical": null,
      "dimensions": [],
      "input_skill": "DDR5",
      "matched_via": null,
      "new_alias_persisted": false,
      "new_alias_text": null,
      "new_skill_meta": {
        "derived": {
          "category": "Memory Technologies",
          "skill_nature": "TOOL",
          "sub_category": "general",
          "typical_lifespan": "MULTI_YEAR",
          "version_strategy": "UNVERSIONED",
          "volatility": "MEDIUM"
        },
        "enrichment": null,
        "keep_log": [],
        "locked_dimensions": [],
        "merge_log": [],
        "placed": null,
        "relationships": null,
        "skill_id": "ddr5",
        "split_log": [],
        "typed": null,
        "warnings": []
      },
      "source_tag": "llm",
      "was_in_llm_skills": true
    },
    {
      "aliases_in_db": [],
      "canonical": null,
      "dimensions": [],
      "input_skill": "GDDR6",
      "matched_via": null,
      "new_alias_persisted": false,
      "new_alias_text": null,
      "new_skill_meta": {
        "derived": {
          "category": "Memory Technologies",
          "skill_nature": "TOOL",
          "sub_category": "general",
          "typical_lifespan": "MULTI_YEAR",
          "version_strategy": "UNVERSIONED",
          "volatility": "MEDIUM"
        },
        "enrichment": null,
        "keep_log": [],
        "locked_dimensions": [],
        "merge_log": [],
        "placed": null,
        "relationships": null,
        "skill_id": "gddr6",
        "split_log": [],
        "typed": null,
        "warnings": []
      },
      "source_tag": "llm",
      "was_in_llm_skills": true
    },
    {
      "aliases_in_db": [],
      "canonical": null,
      "dimensions": [],
      "input_skill": "HBM2",
      "matched_via": null,
      "new_alias_persisted": false,
      "new_alias_text": null,
      "new_skill_meta": {
        "derived": {
          "category": "Memory Technologies",
          "skill_nature": "TOOL",
          "sub_category": "general",
          "typical_lifespan": "MULTI_YEAR",
          "version_strategy": "UNVERSIONED",
          "volatility": "MEDIUM"
        },
        "enrichment": null,
        "keep_log": [],
        "locked_dimensions": [],
        "merge_log": [],
        "placed": null,
        "relationships": null,
        "skill_id": "hbm2",
        "split_log": [],
        "typed": null,
        "warnings": []
      },
      "source_tag": "llm",
      "was_in_llm_skills": true
    },
    {
      "aliases_in_db": [],
      "canonical": null,
      "dimensions": [],
      "input_skill": "HBM3",
      "matched_via": null,
      "new_alias_persisted": false,
      "new_alias_text": null,
      "new_skill_meta": {
        "derived": {
          "category": "Memory Technologies",
          "skill_nature": "TOOL",
          "sub_category": "general",
          "typical_lifespan": "SHORT_LIVED",
          "version_strategy": "VERSIONED",
          "volatility": "FAST"
        },
        "enrichment": null,
        "keep_log": [],
        "locked_dimensions": [],
        "merge_log": [],
        "placed": null,
        "relationships": null,
        "skill_id": "hbm3",
        "split_log": [],
        "typed": null,
        "warnings": []
      },
      "source_tag": "llm",
      "was_in_llm_skills": true
    }
  ],
  "unmatched_skills": [
    "RTL",
    "LPDDR5",
    "DDR5",
    "GDDR6",
    "HBM2",
    "HBM3"
  ]
}

{
  "chosen_role": {
    "display_name": "Frontend Developer",
    "id": 7,
    "rationale": "Exact alias hit on frontend-engineer (1.0) \u2014 no other alias at this confidence; skill_top absent does not contradict",
    "role_archetype": null,
    "slug": "frontend-engineer",
    "source": "db"
  },
  "chosen_role_resolution": "in_db",
  "final_input_skills": [
    {
      "skill": "RTL",
      "tag": "new"
    },
    {
      "skill": "LPDDR5",
      "tag": "new"
    },
    {
      "skill": "DDR5",
      "tag": "new"
    },
    {
      "skill": "GDDR6",
      "tag": "new"
    },
    {
      "skill": "HBM2",
      "tag": "new"
    },
    {
      "skill": "HBM3",
      "tag": "new"
    }
  ],
  "llm_cost_api1_usd": null,
  "llm_cost_api2_usd": null,
  "llm_cost_api3_usd": null,
  "llm_cost_total_usd": null,
  "persistence": {
    "items": [],
    "new_skills_created": 0,
    "role_dimension_saved": 0,
    "skill_dimension_saved": 0,
    "skipped": 0
  },
  "planner_output": null,
  "run_id": "5044a1cf-344b-4676-955a-98d9c1915d09"
}