Pipeline run

fc426b31-1bc9-403c-ab09-4f77f48298fa

Pipeline LLM cost (USD)

API 1: $0.0091 API 2: $0.0016 API 3: $0.0000 Total: $0.0107

Client output enrichment

v2 Skill cluster · Nature of work · AI index · Tech stack maturity · Evidence · KRA description

Nature of work · IP integration / customer support

Guide customers integrating Interface IP into ASIC/SoC designs, reviewing integration milestones, debugging RTL/gate-level issues, and supporting silicon/system bring-up and characterization across the SoC flow.

""provide IIP integration guidance to customers throughout their SoC flow to resolve technical challenges""

Tech stack maturity

Mainstream Modern

AI index (0 = no AI use, 5 = totally AI-dependent · v2.1)

0.00 / 5

· Title match

· Has AI skill

· AI skill (primary)

· AI skill (secondary)

· On AI team

· Builds AI products

vocab breakdown (legacy)

Assistants (×1): —

Frameworks (×2): —

Models / concepts (×3): —

Evidence — skills matched in JD (32)

ASIC SoC Interface IP DDR LPDDR4 LPDDR4x LPDDR5 IP design Simulation Verification RTL synthesis Floor planning Physical design Timing closure Silicon bring-up Characterization PCI Express SERDES Serial ATA RTL Gate Level simulation Synthesis Static Timing Analysis Logical Equivalence Check PCIe +7

Skill cluster (1 dimension groups, role-scoped)

Cross-cutting / unaligned

Show KRA description ↓

This position requires a highly motivated and experienced person to work with Synopsys’ customers on integrating leading edge Interface IP (IIP) into their ASIC SoC/systems for next generation products utilizing our DDR/LPDDR4/4x/5. The position offers opportunities to work on Synopsys IIP and the latest industry specifications/applications on various hot market segments. The position will provide IIP integration guidance to customers throughout their SoC flow to resolve technical challenges, perform integration reviews at key milestones and support silicon/system bring-up. Some travels may be required • This position typically requires at least 2 to 3 years of related IP design or customer experience, but we may also consider candidates with less experience with the right academic background. • ASIC design experience with proven design background. • Experience in one or multiple steps on IP design or integration flow of ASIC / SoC design (such as simulation/verification, RTL synthesis, floor planning, physical design, timing closure, etc.) and silicon bring-up/characterization in a system environment. • Domain knowledge of at least one of the following protocols: • PCI Express • SERDES • Serial ATA • Good RTL and Gate Level simulation Debug skills • Familiarity with Front end implementation like Synthesis, Static Timing Analysis, Logical Equivalence Check • Technical knowledge with any Interface IP such as PCIe, USB, SATA, MIPI, HBM DDR, LPDDR Protocols, Specification, Design, and Implementation flows with Design Compiler, Fusion Compiler and PrimeTrime. • Excellent organization skills, excellent communication skills and ability to interact with customers • Proven track record in meeting tight schedules and handling multiple projects concurrently

Signals

Skill —

—

Alias backend-engineer

1.00

KRA engineering-manager

0.40

Post-classification

Centroidupdated · n=8

Alias collision log—

New-role queue—

New skills captured32

New KRA capturedyes

Captured for admin review

ASIC primary ↔ FPGA / ASIC Engineer pending

SoC primary ↔ FPGA / ASIC Engineer pending

Interface IP primary ↔ FPGA / ASIC Engineer pending

DDR primary ↔ FPGA / ASIC Engineer pending

LPDDR4 primary ↔ FPGA / ASIC Engineer pending

LPDDR4x primary ↔ FPGA / ASIC Engineer pending

LPDDR5 primary ↔ FPGA / ASIC Engineer pending

IP design primary ↔ FPGA / ASIC Engineer pending

Simulation primary ↔ FPGA / ASIC Engineer pending

Verification primary ↔ FPGA / ASIC Engineer pending

RTL synthesis primary ↔ FPGA / ASIC Engineer pending

Floor planning primary ↔ FPGA / ASIC Engineer pending

Physical design primary ↔ FPGA / ASIC Engineer pending

Timing closure primary ↔ FPGA / ASIC Engineer pending

Silicon bring-up primary ↔ FPGA / ASIC Engineer pending

Characterization primary ↔ FPGA / ASIC Engineer pending

PCI Express primary ↔ FPGA / ASIC Engineer pending

SERDES primary ↔ FPGA / ASIC Engineer pending

Serial ATA primary ↔ FPGA / ASIC Engineer pending

RTL primary ↔ FPGA / ASIC Engineer pending

Gate Level simulation primary ↔ FPGA / ASIC Engineer pending

Synthesis primary ↔ FPGA / ASIC Engineer pending

Static Timing Analysis primary ↔ FPGA / ASIC Engineer pending

Logical Equivalence Check primary ↔ FPGA / ASIC Engineer pending

PCIe primary ↔ FPGA / ASIC Engineer pending

USB primary ↔ FPGA / ASIC Engineer pending

SATA primary ↔ FPGA / ASIC Engineer pending

MIPI primary ↔ FPGA / ASIC Engineer pending

HBM primary ↔ FPGA / ASIC Engineer pending

Design Compiler primary ↔ FPGA / ASIC Engineer pending

Fusion Compiler primary ↔ FPGA / ASIC Engineer pending

PrimeTime primary ↔ FPGA / ASIC Engineer pending

R&R fragment (sim 0.00) ↔ FPGA / ASIC Engineer pending

Status: completed Created: 2026-05-27T17:40:25.561731Z Updated: 2026-05-27T17:43:23.681618Z API 3 duration: 1047 ms

Flow Current 3-step pipeline

1 POST /skills/extract-from-jd

2 POST /skills/extract-details

3 POST /skills/final-role-output

Role Chosen role & resolution

FPGA / ASIC Engineer

domain · Hardware Engineering CASE DOMAIN

slug: fpga-asic-engineer · id: 216 · source: db

Domain=Hardware Engineering; The JD is centered on ASIC/SoC IP integration, RTL/synthesis/timing, verification, and silicon bring-up, which best matches FPGA / ASIC Engineer.

Matched skills

Interface IPDDR/LPDDR4/4x/5ASICSoCPCI ExpressSERDESSerial ATARTLGate Level simulationSynthesisStatic Timing AnalysisLogical Equivalence CheckDesign CompilerFusion CompilerPrimeTrime

Matched dimensions

IP IntegrationASIC/SoC DesignSimulation and VerificationPhysical Design and Timing ClosureSilicon Bring-up and CharacterizationCustomer Technical SupportCross-functional Communication

Matched KRAs

work with Synopsys’ customers on integrating leading edge Interface IPprovide IIP integration guidance to customers throughout their SoC flowresolve technical challengesperform integration reviews at key milestonessupport silicon/system bring-upwork on Synopsys IIP and the latest industry specifications/applications

Resolution: in_db — role exists in library; skill↔dim and role↔dim links saved when applicable.

New skills

Skill↔dim saved

Role↔dim saved

Skipped

Job description

Job Description And Requirements

This position requires a highly motivated and experienced person to work with Synopsys’ customers on integrating leading edge Interface IP (IIP) into their ASIC SoC/systems for next generation products utilizing our DDR/LPDDR4/4x/5. The position offers opportunities to work on Synopsys IIP and the latest industry specifications/applications on various hot market segments. The position will provide IIP integration guidance to customers throughout their SoC flow to resolve technical challenges, perform integration reviews at key milestones and support silicon/system bring-up. Some travels may be required

Key Qualifications:

• This position typically requires at least 2 to 3 years of related IP design or customer experience, but we may also consider candidates with less experience with the right academic background.
• ASIC design experience with proven design background.
• Experience in one or multiple steps on IP design or integration flow of ASIC / SoC design (such as simulation/verification, RTL synthesis, floor planning, physical design, timing closure, etc.) and silicon bring-up/characterization in a system environment.
• Domain knowledge of at least one of the following protocols:
• PCI Express
• SERDES
• Serial ATA
• Good RTL and Gate Level simulation Debug skills
• Familiarity with Front end implementation like Synthesis, Static Timing Analysis, Logical Equivalence Check


Preferred Experience

• Technical knowledge with any Interface IP such as PCIe, USB, SATA, MIPI, HBM DDR, LPDDR Protocols, Specification, Design, and Implementation flows with Design Compiler, Fusion Compiler and PrimeTrime.
• Excellent organization skills, excellent communication skills and ability to interact with customers
• Proven track record in meeting tight schedules and handling multiple projects concurrently


Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Job Category

Engineering

Country

India

Job Subcategory

Applications Engineering

Hire Type

Employee

Skills from this JD

Each row merges API 1 extraction, API 2 library match / v3 orchestration (dimensions + locked dims), and API 3 persistence tags.

ASIC Primary New / orchestrated API 3: new canonical path (new) New / unmatched skill (orchestrated in API 2)

Skill enrichment (orchestrator / LLM)